A motivated Senior DFT Engineer with 10+ years of hands-on experience in DFT implementation who will participate to the design of a state-of-the-art CMOS Transceiver ASIC for the Communications market. The candidate will drive and execute the definition and implementation of DFT in the chip in closed relationship with the physical implementation as well industrialization teams.

The project is based in Paris, France, full remote, permanent contract, start date, immediately.

Desired skills:

• Good knowledge in RTL design
• TLC, Perl or Python
• Experience in ATPG, BIST, ECC & Redundancy
• Experience with ASIC test methods
• Cadence DFT design flow (Genus, Modus)

If you are interested in this position, please apply or send your updated CV to (see below) for immediate consideration.